// **************************************************************
// Copyright (c) 2021 Xidian University.
// File name     : np_misc.v
// Module name   : 
// Created Date  : 2022-05-03
// Author        : 
// Email         : 
// -------------------------------------------------------------------------
// Version       : 
// Last Modified : 2022-07-01
// Modified By   : Wangzekun
// -------------------------------------------------------------------------
// 
// -------------------------------------------------------------------------
// HISTORY       : v1.0/v1.1/v2.0/v2.1
// Date         By  Comments
// ------------ --  ----------------------------------------------------------
// v1.0
// v1.1 
// v2.0
// v2.1   mbist_test
// v2.2   to wait phy ack, modify hreadyout
// 
// **************************************************************
`include "top_define.v"
module np_misc 
 (
  input  wire         ahbclk      ,
  input  wire         ahbresetn   ,
  input  wire         pkt_rstn    ,
  input  wire         pkt_clk     ,
    // input            arstn_mac1,
    // input            arstn_mac2, 

// JTAG interface
  input  wire         jtag_clk     ,
  //input  wire         jtag_clk_n,
  input  wire         jtag_trst    ,
  input  wire         jtag_tms     ,
  input  wire         jtag_tdi     ,
  output wire         jtag_tdo     ,
  output wire         jtag_tdo_en  ,

//ahb_cfg
  input  wire [31:0]  haddr_ahbm      ,
  input  wire [2:0]   hburst_ahbm     ,
  input  wire [3:0]   hprot_ahbm      ,
  input  wire [2:0]   hsize_ahbm      ,
  input  wire [1:0]   htrans_ahbm     ,
  input  wire [31:0]  hwdata_ahbm     ,
  input  wire         hwrite_ahbm     ,
  input  wire         hselx_ahbm      ,
  input  wire         hready_ahbm     ,
  output wire [31:0]  hrdata_ahbm     ,
  output wire         hreadyout_ahbm  ,
  output wire         hresp_ahbm      ,

   
   //phy power
   
`ifdef SIM
  input  wire         bus0_axi_valid_i,
  input  wire [255:0] bus0_axi_data_i ,
  input  wire         bus0_axi_last_i ,
  input  wire [ 31:0] bus0_axi_keep_i ,
  output wire         bus0_axi_ready_i,
  
  input  wire         bus1_axi_valid_i,
  input  wire [255:0] bus1_axi_data_i ,
  input  wire         bus1_axi_last_i ,
  input  wire [ 31:0] bus1_axi_keep_i ,
  output wire         bus1_axi_ready_i,
  
  input  wire         bus2_axi_valid_i,
  input  wire [255:0] bus2_axi_data_i ,
  input  wire         bus2_axi_last_i ,
  input  wire [ 31:0] bus2_axi_keep_i ,
  output wire         bus2_axi_ready_i,
  
  input  wire         bus3_axi_valid_i,
  input  wire [255:0] bus3_axi_data_i ,
  input  wire         bus3_axi_last_i ,
  input  wire [ 31:0] bus3_axi_keep_i ,
  output wire         bus3_axi_ready_i,
`endif
   
`ifdef CPU
  output          CPU_SRAM_wren       ,
  output          CPU_SRAM_rden       ,
  output   [31:0] CPU_SRAM_wdata      ,
  output   [15:0] CPU_SRAM_addr       ,
  input    [31:0] CPU_SRAM_rdata      ,
  input           CPU_SRAM_rdata_vld  ,
  
  output reg [31:0]cpu_rstn_register              ,
  output reg [5:0] cpu_rxd_register               ,
  output reg [1:0] cpu_gpi_register               ,
  output reg [13:0]cpu_spi_register               ,
  output reg [10:0]cpu_fuse_register              ,
  output reg [95:0]cpu_if_data_adc_d_i_register   ,
`endif
   // output reg [ 9:0]io_pullup_cfg_register    ,
   // output reg [ 9:0]io_pulldown_cfg_register  ,

//********************************************************************
// UDP config channel signal
  // clock in
  input  wire                           clk_100M                    , // UDP deal main clock
  input  wire                           clk_125M                    , // be used to send RGMII_txd data
  input  wire                           clk_125M_90phase            , // 90-phase delay from "clk_125M"
  input  wire                           dcm_locked                  , // PLL locked flag
  // PHY interface
  output wire                           phyrst_n                    , // PHY chip reset
  // RGMII receive channel
  input  wire                           rgmii_rx_clk                ,
  input  wire                           rgmii_rx_ctrl               ,
  input  wire [3:0]                     rgmii_rxd                   ,
  // RGMII send channel
  output wire                           rgmii_tx_clk                ,
  output wire                           rgmii_tx_ctrl               ,
  output wire [3:0]                     rgmii_txd                   ,
//********************************************************************
  input  wire                           external_ahb_select          , // mask the UDP channel

//--------------------------------------------------------------------
//double_bus
//--------------------------------------------------------------------
output wire [16:0]    bus1_phy_ctrl_register             ,
output wire [25:0]    bus1_reset_register                ,
output wire [ 8:0]    bus1_req_lb_register               ,
input  wire [ 8:0]    bus1_ack_register_temp             ,
output wire [11:0]    bus1_mac_pcs_status_register1      ,
input  wire [27:0]    bus1_mac_pcs_status_register0_temp ,
input  wire [16:0]    bus1_mac_pcs_status_register2_temp ,

output wire [16:0]    bus2_phy_ctrl_register             ,
output wire [25:0]    bus2_reset_register                ,
output wire [ 8:0]    bus2_req_lb_register               ,
input  wire [ 8:0]    bus2_ack_register_temp             ,
output wire [11:0]    bus2_mac_pcs_status_register1      ,
input  wire [27:0]    bus2_mac_pcs_status_register0_temp ,
input  wire [16:0]    bus2_mac_pcs_status_register2_temp ,

output wire [16:0]    bus3_phy_ctrl_register             ,
output wire [25:0]    bus3_reset_register                ,
output wire [ 8:0]    bus3_req_lb_register               ,
input  wire [ 8:0]    bus3_ack_register_temp             ,
output wire [11:0]    bus3_mac_pcs_status_register1      ,
input  wire [27:0]    bus3_mac_pcs_status_register0_temp ,
input  wire [16:0]    bus3_mac_pcs_status_register2_temp ,

output wire [16:0]    bus4_phy_ctrl_register             ,
output wire [25:0]    bus4_reset_register                ,
output wire [ 8:0]    bus4_req_lb_register               ,
input  wire [ 8:0]    bus4_ack_register_temp             ,
output wire [11:0]    bus4_mac_pcs_status_register1      ,
input  wire [27:0]    bus4_mac_pcs_status_register0_temp ,
input  wire [16:0]    bus4_mac_pcs_status_register2_temp ,

input wire    phy_jtag_tdo_0    ,
input wire    phy_jtag_tdo_en_0 ,
input wire    phy_jtag_tdo_1    ,
input wire    phy_jtag_tdo_en_1 ,
input wire    phy_jtag_tdo_2    ,
input wire    phy_jtag_tdo_en_2 ,
input wire    phy_jtag_tdo_3    ,
input wire    phy_jtag_tdo_en_3 ,

output wire   phy_jtag_tdi_0 ,
output wire   phy_jtag_tdi_1 ,
output wire   phy_jtag_tdi_2 ,
output wire   phy_jtag_tdi_3 ,

output wire           bus1_xpcs_reg_wren       ,
output wire           bus1_xpcs_reg_rden       ,
output wire [15:0]    bus1_xpcs_reg_addr       ,
output wire [15:0]    bus1_xpcs_reg_din        ,
input  wire [15:0]    bus1_xpcs_reg_dout       ,
input  wire           bus1_xpcs_reg_busy       ,
output wire           bus2_xpcs_reg_wren       ,
output wire           bus2_xpcs_reg_rden       ,
output wire [15:0]    bus2_xpcs_reg_addr       ,
output wire [15:0]    bus2_xpcs_reg_din        ,
input  wire [15:0]    bus2_xpcs_reg_dout       ,
input  wire           bus2_xpcs_reg_busy       ,
output wire           bus3_xpcs_reg_wren       ,
output wire           bus3_xpcs_reg_rden       ,
output wire [15:0]    bus3_xpcs_reg_addr       ,
output wire [15:0]    bus3_xpcs_reg_din        ,
input  wire [15:0]    bus3_xpcs_reg_dout       ,
input  wire           bus3_xpcs_reg_busy       ,
output wire           bus4_xpcs_reg_wren       ,
output wire           bus4_xpcs_reg_rden       ,
output wire [15:0]    bus4_xpcs_reg_addr       ,
output wire [15:0]    bus4_xpcs_reg_din        ,
input  wire [15:0]    bus4_xpcs_reg_dout       ,
input  wire           bus4_xpcs_reg_busy       ,

output wire           bus1_xlpcs_reg_wren       ,
output wire           bus1_xlpcs_reg_rden       ,
output wire [15:0]    bus1_xlpcs_reg_addr       ,
output wire [15:0]    bus1_xlpcs_reg_din        ,
input  wire [15:0]    bus1_xlpcs_reg_dout       ,
input  wire           bus1_xlpcs_reg_busy       ,
output wire           bus2_xlpcs_reg_wren       ,
output wire           bus2_xlpcs_reg_rden       ,
output wire [15:0]    bus2_xlpcs_reg_addr       ,
output wire [15:0]    bus2_xlpcs_reg_din        ,
input  wire [15:0]    bus2_xlpcs_reg_dout       ,
input  wire           bus2_xlpcs_reg_busy       ,
output wire           bus3_xlpcs_reg_wren       ,
output wire           bus3_xlpcs_reg_rden       ,
output wire [15:0]    bus3_xlpcs_reg_addr       ,
output wire [15:0]    bus3_xlpcs_reg_din        ,
input  wire [15:0]    bus3_xlpcs_reg_dout       ,
input  wire           bus3_xlpcs_reg_busy       ,
output wire           bus4_xlpcs_reg_wren       ,
output wire           bus4_xlpcs_reg_rden       ,
output wire [15:0]    bus4_xlpcs_reg_addr       ,
output wire [15:0]    bus4_xlpcs_reg_din        ,
input  wire [15:0]    bus4_xlpcs_reg_dout       ,
input  wire           bus4_xlpcs_reg_busy       ,

output wire           bus1_mac_reg_wren         ,
output wire           bus1_mac_reg_rden         ,
output wire [ 7:0]    bus1_mac_reg_addr         ,
output wire [31:0]    bus1_mac_reg_din          ,
input  wire [31:0]    bus1_mac_reg_dout         ,
input  wire           bus1_mac_reg_busy         ,
output wire           bus2_mac_reg_wren         ,
output wire           bus2_mac_reg_rden         ,
output wire [ 7:0]    bus2_mac_reg_addr         ,
output wire [31:0]    bus2_mac_reg_din          ,
input  wire [31:0]    bus2_mac_reg_dout         ,
input  wire           bus2_mac_reg_busy         ,
output wire           bus3_mac_reg_wren         ,
output wire           bus3_mac_reg_rden         ,
output wire [ 7:0]    bus3_mac_reg_addr         ,
output wire [31:0]    bus3_mac_reg_din          ,
input  wire [31:0]    bus3_mac_reg_dout         ,
input  wire           bus3_mac_reg_busy         ,
output wire           bus4_mac_reg_wren         ,
output wire           bus4_mac_reg_rden         ,
output wire [ 7:0]    bus4_mac_reg_addr         ,
output wire [31:0]    bus4_mac_reg_din          ,
input  wire [31:0]    bus4_mac_reg_dout         ,
input  wire           bus4_mac_reg_busy         ,

input  wire [63:0]    bus1_mac_tx_ts           ,
output wire [63:0]    bus1_mac_frc_in_tx       ,
output wire [63:0]    bus1_mac_frc_in_rx       ,
input  wire [63:0]    bus2_mac_tx_ts           ,
output wire [63:0]    bus2_mac_frc_in_tx       ,
output wire [63:0]    bus2_mac_frc_in_rx       ,
input  wire [63:0]    bus3_mac_tx_ts           ,
output wire [63:0]    bus3_mac_frc_in_tx       ,
output wire [63:0]    bus3_mac_frc_in_rx       ,
input  wire [63:0]    bus4_mac_tx_ts           ,
output wire [63:0]    bus4_mac_frc_in_tx       ,
output wire [63:0]    bus4_mac_frc_in_rx       ,

input  wire  fp_sch_init_done0 ,
input  wire  fp_sch_init_done1 ,
input  wire  fp_sch_init_done2 ,
input  wire  fp_sch_init_done3 ,

output wire        npsys_wr_in_bus1         ,
output wire        npsys_rd_in_bus1         ,
input  wire [31:0] bus1_npsys_data_out      ,
input  wire        bus1_npsys_data_out_vld  ,
output wire        npsys_wr_in_bus2         ,
output wire        npsys_rd_in_bus2         ,
input  wire [31:0] bus2_npsys_data_out      ,
input  wire        bus2_npsys_data_out_vld  ,
output wire        npsys_wr_in_bus3         ,
output wire        npsys_rd_in_bus3         ,
input  wire [31:0] bus3_npsys_data_out      ,
input  wire        bus3_npsys_data_out_vld  ,
output wire        npsys_wr_in_bus4         ,
output wire        npsys_rd_in_bus4         ,
input  wire [31:0] bus4_npsys_data_out      ,
input  wire        bus4_npsys_data_out_vld  ,

output wire uni_tx_rdy00 ,
output wire uni_tx_rdy01 ,
output wire uni_tx_rdy02 ,
output wire uni_tx_rdy03 ,
output wire mul_tx_rdy00 ,
output wire mul_tx_rdy01 ,
output wire mul_tx_rdy02 ,
output wire mul_tx_rdy03 ,
output wire uni_tx_rdy10 ,
output wire uni_tx_rdy11 ,
output wire uni_tx_rdy12 ,
output wire uni_tx_rdy13 ,
output wire mul_tx_rdy10 ,
output wire mul_tx_rdy11 ,
output wire mul_tx_rdy12 ,
output wire mul_tx_rdy13 ,
output wire uni_tx_rdy20 ,
output wire uni_tx_rdy21 ,
output wire uni_tx_rdy22 ,
output wire uni_tx_rdy23 ,
output wire mul_tx_rdy20 ,
output wire mul_tx_rdy21 ,
output wire mul_tx_rdy22 ,
output wire mul_tx_rdy23 ,
output wire uni_tx_rdy30 ,
output wire uni_tx_rdy31 ,
output wire uni_tx_rdy32 ,
output wire uni_tx_rdy33 ,
output wire mul_tx_rdy30 ,
output wire mul_tx_rdy31 ,
output wire mul_tx_rdy32 ,
output wire mul_tx_rdy33 ,

input  wire [255:0] emac_data_in0     ,
input  wire         emac_data_wren0   ,
input  wire [  5:0] rx_address_dpram0 ,
input  wire [  3:0] mac_dest_port_in0 ,
input  wire         mul_indicate0     ,
input  wire [255:0] emac_data_in1     ,
input  wire         emac_data_wren1   ,
input  wire [  5:0] rx_address_dpram1 ,
input  wire [  3:0] mac_dest_port_in1 ,
input  wire         mul_indicate1     ,
input  wire [255:0] emac_data_in2     ,
input  wire         emac_data_wren2   ,
input  wire [  5:0] rx_address_dpram2 ,
input  wire [  3:0] mac_dest_port_in2 ,
input  wire         mul_indicate2     ,
input  wire [255:0] emac_data_in3     ,
input  wire         emac_data_wren3   ,
input  wire [  5:0] rx_address_dpram3 ,
input  wire [  3:0] mac_dest_port_in3 ,
input  wire         mul_indicate3     ,

output wire           pkt_sop_i_40_0  ,
output wire [255:0]   pkt_data_i_40_0 ,
output wire           pkt_eop_i_40_0  ,
output wire [4:0]     pkt_mod_i_40_0  ,
output wire           pkt_dval_i_40_0 ,
output wire           pkt_sop_i_40_1  ,
output wire [255:0]   pkt_data_i_40_1 ,
output wire           pkt_eop_i_40_1  ,
output wire [4:0]     pkt_mod_i_40_1  ,
output wire           pkt_dval_i_40_1 ,
output wire           pkt_sop_i_10_0  ,
output wire [255:0]   pkt_data_i_10_0 ,
output wire           pkt_eop_i_10_0  ,
output wire [4:0]     pkt_mod_i_10_0  ,
output wire           pkt_dval_i_10_0 ,
output wire           pkt_sop_i_10_1  ,
output wire [255:0]   pkt_data_i_10_1 ,
output wire           pkt_eop_i_10_1  ,
output wire [4:0]     pkt_mod_i_10_1  ,
output wire           pkt_dval_i_10_1 ,

input  wire emac_rx_ready0 ,
input  wire emac_rx_ready1 ,
input  wire emac_rx_ready2 ,
input  wire emac_rx_ready3 ,

output wire [31:0]     npsys_data_in,
output wire [16:0]     npsys_addr_in,
output wire [31:0]     npsys_data_in_1,
output wire [16:0]     npsys_addr_in_1,

output wire [9 :0]      ram_2p_cfg_out_0,
output wire [11:0]      ram_dp_cfg_out_0,
output wire [6 :0]      rf_2p_cfg_out_0,

output wire [9 :0]      ram_2p_cfg_out_1,
output wire [11:0]      ram_dp_cfg_out_1,
output wire [6 :0]      rf_2p_cfg_out_1,

//output wire            np_hselx_ahbm    ,
//output wire            np_hready_ahbm   ,
//output wire [1:0]      np_htrans_ahbm   ,
//output wire [2:0]      np_hsize_ahbm    ,
//output wire            np_hwrite_ahbm   ,
//output wire [31:0]     np_haddr_ahbm    ,
//output wire [31:0]     np_hwdata_ahbm   ,
//
//input wire [31:0] hrdata_np_dma_0 ,
//input wire [31:0] hrdata_np_dma_1 ,

output wire [1:0] dma_channel_sel0,
output wire [1:0] dma_channel_sel1,

// DFT port
input wire mbist_test,
input wire scan_mode,
input wire scan_set_rst

); 


//parameter
parameter SLAVE_NUM = 26;

// wire  [15:0]np_addr_in_d2;
// wire [SLAVE_NUM*2+1:0]  bus1_np_addr_ctrl;
// wire [SLAVE_NUM*2-1:0]  bus2_np_addr_ctrl;
// wire [SLAVE_NUM*2-1:0]  bus3_np_addr_ctrl;
// wire [SLAVE_NUM*2-1:0]  bus4_np_addr_ctrl;
//
//----------------------------------------------------------
wire [18:0]phy_mac_addr_in     ;
wire [31:0]phy_mac_data_in     ;
wire [31:0]phy_mac_data_out    ;
wire       phy_mac_data_out_vld;
wire       phy_mac_wr;
wire       phy_mac_rd;
//---------------------------------------------------------
// wire [31:0]np_data_in_config;
// wire [31:0]np_addr_in_config;
// wire np_wr_config;
// wire np_rd_config;
// wire np_sel_en_config;

reg  [31:0] CPU_reg_rdata;
reg         CPU_reg_rdata_vld;
reg  [31:0] np_addr_in_d1;
reg         CPU_reg_rden_d1;
reg         CPU_reg_wren;
reg         CPU_reg_rden;

wire [3:0] config_done;
assign config_done = {fp_sch_init_done3,fp_sch_init_done2,fp_sch_init_done1,fp_sch_init_done0};

reg  [31:0] np_data_out         ;
reg  [31:0] np_data_in          ;
reg  [31:0] np_addr_in          ;
reg         np_wr               ;
reg         np_rd               ;
reg  [31:0] np_data_in_1        ;
reg  [31:0] np_addr_in_1        ;

reg         np_sel_en           ;

wire [31:0] jtag_cfg_addr_o     ;
wire [31:0] jtag_cfg_wr_data_o  ;
wire        jtag_cfg_wr_en_o    ;
wire        jtag_cfg_rd_en_o    ;
reg  [31:0] jtag_cfg_rd_data_i  ;
wire        jtag_occupy         ;

  reg   [31:0]  np_data_in_d1;
  // reg   [31:0]  np_data_in_d1,np_data_in_d2;
  reg   [31:0]  ahb_cfg_rd_data_i;
  wire  [31:0]  ahb_cfg_addr_o;
  wire  [31:0]  ahb_cfg_wr_data_o;
  wire          ahb_cfg_wr_en_o;
  wire          ahb_cfg_rd_en_o;

wire [ 8:0]bus1_ack_register;
wire [27:0]bus1_mac_pcs_status_register0;
wire [16:0]bus1_mac_pcs_status_register2;
wire [31:0]bus1_mac_pcs_status_register7;
wire [31:0]bus1_mac_pcs_status_register8;
wire [31:0]bus1_mac_pcs_status_register7_temp;
wire [31:0]bus1_mac_pcs_status_register8_temp;
wire [31:0]bus1_mac_pcs_status_register3;
wire [31:0]bus1_mac_pcs_status_register4;
wire [31:0]bus1_mac_pcs_status_register5;
wire [31:0]bus1_mac_pcs_status_register6;
wire [ 8:0]bus2_ack_register;
wire [27:0]bus2_mac_pcs_status_register0;
wire [16:0]bus2_mac_pcs_status_register2;
wire [31:0]bus2_mac_pcs_status_register7;
wire [31:0]bus2_mac_pcs_status_register8;
wire [31:0]bus2_mac_pcs_status_register7_temp;
wire [31:0]bus2_mac_pcs_status_register8_temp;
wire [31:0]bus2_mac_pcs_status_register3;
wire [31:0]bus2_mac_pcs_status_register4;
wire [31:0]bus2_mac_pcs_status_register5;
wire [31:0]bus2_mac_pcs_status_register6;
wire [ 8:0]bus3_ack_register;
wire [27:0]bus3_mac_pcs_status_register0;
wire [16:0]bus3_mac_pcs_status_register2;
wire [31:0]bus3_mac_pcs_status_register7;
wire [31:0]bus3_mac_pcs_status_register8;
wire [31:0]bus3_mac_pcs_status_register7_temp;
wire [31:0]bus3_mac_pcs_status_register8_temp;
wire [31:0]bus3_mac_pcs_status_register3;
wire [31:0]bus3_mac_pcs_status_register4;
wire [31:0]bus3_mac_pcs_status_register5;
wire [31:0]bus3_mac_pcs_status_register6;
wire [ 8:0]bus4_ack_register;
wire [27:0]bus4_mac_pcs_status_register0;
wire [16:0]bus4_mac_pcs_status_register2;
wire [31:0]bus4_mac_pcs_status_register7;
wire [31:0]bus4_mac_pcs_status_register8;
wire [31:0]bus4_mac_pcs_status_register7_temp;
wire [31:0]bus4_mac_pcs_status_register8_temp;
wire [31:0]bus4_mac_pcs_status_register3;
wire [31:0]bus4_mac_pcs_status_register4;
wire [31:0]bus4_mac_pcs_status_register5;
wire [31:0]bus4_mac_pcs_status_register6;

reg [9 :0]      ram_2p_cfg_register;
reg [11:0]      ram_dp_cfg_register;
reg [6 :0]      rf_2p_cfg_register;
reg [9 :0]      ram_2p_cfg_register_1;
reg [11:0]      ram_dp_cfg_register_1;
reg [6 :0]      rf_2p_cfg_register_1;

assign {bus1_mac_pcs_status_register7_temp,bus1_mac_pcs_status_register8_temp} = bus1_mac_tx_ts ; // input
assign {bus2_mac_pcs_status_register7_temp,bus2_mac_pcs_status_register8_temp} = bus2_mac_tx_ts ; // input
assign {bus3_mac_pcs_status_register7_temp,bus3_mac_pcs_status_register8_temp} = bus3_mac_tx_ts ; // input
assign {bus4_mac_pcs_status_register7_temp,bus4_mac_pcs_status_register8_temp} = bus4_mac_tx_ts ; // input
assign bus1_mac_frc_in_tx = {bus1_mac_pcs_status_register3,bus1_mac_pcs_status_register4}       ; // output
assign bus1_mac_frc_in_rx = {bus1_mac_pcs_status_register5,bus1_mac_pcs_status_register6}       ; // output
assign bus2_mac_frc_in_tx = {bus2_mac_pcs_status_register3,bus2_mac_pcs_status_register4}       ; // output
assign bus2_mac_frc_in_rx = {bus2_mac_pcs_status_register5,bus2_mac_pcs_status_register6}       ; // output
assign bus3_mac_frc_in_tx = {bus3_mac_pcs_status_register3,bus3_mac_pcs_status_register4}       ; // output
assign bus3_mac_frc_in_rx = {bus3_mac_pcs_status_register5,bus3_mac_pcs_status_register6}       ; // output
assign bus4_mac_frc_in_tx = {bus4_mac_pcs_status_register3,bus4_mac_pcs_status_register4}       ; // output
assign bus4_mac_frc_in_rx = {bus4_mac_pcs_status_register5,bus4_mac_pcs_status_register6}       ; // output

// assign {bus1_mac_pcs_status_register7_temp,bus1_mac_pcs_status_register8_temp} = bus1_mac_tx_ts      ;
// assign {bus1_mac_pcs_status_register3,bus1_mac_pcs_status_register4}           = bus1_mac_frc_in_tx  ;
// assign {bus1_mac_pcs_status_register5,bus1_mac_pcs_status_register6}           = bus1_mac_frc_in_rx  ;
// assign {bus2_mac_pcs_status_register7_temp,bus2_mac_pcs_status_register8_temp} = bus2_mac_tx_ts      ;
// assign {bus2_mac_pcs_status_register3,bus2_mac_pcs_status_register4}           = bus2_mac_frc_in_tx  ;
// assign {bus2_mac_pcs_status_register5,bus2_mac_pcs_status_register6}           = bus2_mac_frc_in_rx  ;
// assign {bus3_mac_pcs_status_register7_temp,bus3_mac_pcs_status_register8_temp} = bus3_mac_tx_ts      ;
// assign {bus3_mac_pcs_status_register3,bus3_mac_pcs_status_register4}           = bus3_mac_frc_in_tx  ;
// assign {bus3_mac_pcs_status_register5,bus3_mac_pcs_status_register6}           = bus3_mac_frc_in_rx  ;
// assign {bus4_mac_pcs_status_register7_temp,bus4_mac_pcs_status_register8_temp} = bus4_mac_tx_ts      ;
// assign {bus4_mac_pcs_status_register3,bus4_mac_pcs_status_register4}           = bus4_mac_frc_in_tx  ;
// assign {bus4_mac_pcs_status_register5,bus4_mac_pcs_status_register6}           = bus4_mac_frc_in_rx  ;

wire    jtag_tdo_np;
wire    jtag_tdo_en_np;

assign phy_jtag_tdi_0 = jtag_tdo_np && jtag_tdo_en_np;
assign phy_jtag_tdi_1 = phy_jtag_tdo_0 && phy_jtag_tdo_en_0;
assign phy_jtag_tdi_2 = phy_jtag_tdo_1 && phy_jtag_tdo_en_1;
assign phy_jtag_tdi_3 = phy_jtag_tdo_2 && phy_jtag_tdo_en_2;
assign jtag_tdo = phy_jtag_tdo_3;
assign jtag_tdo_en = phy_jtag_tdo_en_3;
//assign jtag_tdo = jtag_tdo_np;
//assign jtag_tdo_en = jtag_tdo_en_np;

// wire           pkt_test_sop_0   ;
// wire           pkt_test_dvld_0  ;
// wire           pkt_test_dsav_0  ;
// wire [255:0]   pkt_test_data_0  ;
// wire           pkt_test_eop_0   ;

// wire           pkt_test_sop_1   ;
// wire           pkt_test_dvld_1  ;
// wire           pkt_test_dsav_1  ;
// wire [255:0]   pkt_test_data_1  ;
// wire           pkt_test_eop_1   ;

// wire           pkt_test_sop_2   ;
// wire           pkt_test_dvld_2  ;
// wire           pkt_test_dsav_2  ;
// wire [255:0]   pkt_test_data_2  ;
// wire           pkt_test_eop_2   ;

// wire           pkt_test_sop_3   ;
// wire           pkt_test_dvld_3  ;
// wire           pkt_test_dsav_3  ;
// wire [255:0]   pkt_test_data_3  ;
// wire           pkt_test_eop_3   ;

// wire [255:0]  pkt_data_o_40_0   ;
// wire          pkt_eop_o_40_0    ;
// wire [4:0]    pkt_mod_o_40_0    ;
// wire          pkt_sop_o_40_0    ;
// wire          pkt_dval_o_40_0   ;
// wire          pkt_dsav_o_40_0   ;

// wire [255:0]  pkt_data_o_40_1   ;
// wire          pkt_eop_o_40_1    ;
// wire [4:0]    pkt_mod_o_40_1    ;
// wire          pkt_sop_o_40_1    ;
// wire          pkt_dval_o_40_1   ;
// wire          pkt_dsav_o_40_1   ;

// wire [255:0]  pkt_data_o_10_0   ;
// wire          pkt_eop_o_10_0    ;
// wire [4:0]    pkt_mod_o_10_0    ;
// wire          pkt_sop_o_10_0    ;
// wire          pkt_dval_o_10_0   ;
// wire          pkt_dsav_o_10_0   ;


// wire [255:0]  pkt_data_o_10_1   ;
// wire          pkt_eop_o_10_1    ;
// wire [4:0]    pkt_mod_o_10_1    ;
// wire          pkt_sop_o_10_1    ;
// wire          pkt_dval_o_10_1   ;
// wire          pkt_dsav_o_10_1   ;


// wire [255:0]  mac_data_o_40_0   ;
// wire          mac_eop_o_40_0    ;
// wire [4:0]    mac_mod_o_40_0    ;
// wire          mac_sop_o_40_0    ;
// wire          mac_dval_o_40_0   ;
// wire          mac_dsav_o_40_0   ;

// wire [255:0]  mac_data_i_40_0   ;
// wire          mac_eop_i_40_0    ;
// wire [4:0]    mac_mod_i_40_0    ;
// wire          mac_sop_i_40_0    ;
// wire          mac_dval_i_40_0   ;
// wire [255:0]  mac_data_o_40_1   ;
// wire          mac_eop_o_40_1    ;
// wire [4:0]    mac_mod_o_40_1    ;
// wire          mac_sop_o_40_1    ;
// wire          mac_dval_o_40_1   ;
// wire          mac_dsav_o_40_1   ;

// wire [255:0]  mac_data_i_40_1   ;
// wire          mac_eop_i_40_1    ;
// wire [4:0]    mac_mod_i_40_1    ;
// wire          mac_sop_i_40_1    ;
// wire          mac_dval_i_40_1   ;

// wire [255:0]  mac_data_o_10_0   ;
// wire          mac_eop_o_10_0    ;
// wire [4:0]    mac_mod_o_10_0    ;
// wire          mac_sop_o_10_0    ;
// wire          mac_dval_o_10_0   ;
// wire          mac_dsav_o_10_0   ;

// wire [255:0]  mac_data_i_10_0   ;
// wire          mac_eop_i_10_0    ;
// wire [4:0]    mac_mod_i_10_0    ;
// wire          mac_sop_i_10_0    ;
// wire          mac_dval_i_10_0   ;

// wire [255:0]  mac_data_o_10_1   ;
// wire          mac_eop_o_10_1    ;
// wire [4:0]    mac_mod_o_10_1    ;
// wire          mac_sop_o_10_1    ;
// wire          mac_dval_o_10_1   ;
// wire          mac_dsav_o_10_1   ;

// wire [255:0]  mac_data_i_10_1   ;
// wire          mac_eop_i_10_1    ;
// wire [4:0]    mac_mod_i_10_1    ;
// wire          mac_sop_i_10_1    ;
// wire          mac_dval_i_10_1   ;

wire rx_rdy_mac0;
wire rx_rdy_mac1;
wire rx_rdy_mac2;
wire rx_rdy_mac3;

reg  bus0_mac_rx2tx_loop_en_temp;
reg  bus0_mac_rx2tx_loop_en     ;
reg  bus1_mac_rx2tx_loop_en_temp;
reg  bus1_mac_rx2tx_loop_en     ;
reg  bus2_mac_rx2tx_loop_en_temp;
reg  bus2_mac_rx2tx_loop_en     ;
reg  bus3_mac_rx2tx_loop_en_temp;
reg  bus3_mac_rx2tx_loop_en     ;

wire       bus0_axi_ttvalid;
wire       bus0_axi_ttlast ;
wire [ 7:0]bus0_axi_ttkeep ;
wire [63:0]bus0_axi_ttdata ;
wire       bus0_axi_ttready;
//wire [ 6:0]bus0_axi_ttuser ;
wire       bus0_axi_rtvalid;
wire       bus0_axi_rtlast ;
wire [ 7:0]bus0_axi_rtkeep ;
wire [63:0]bus0_axi_rtdata ;
wire [89:0]bus0_axi_rtuser ;
wire       bus0_axi_rtready;
wire       np_bus0_axi_rtready;
wire       bus1_axi_ttvalid;
wire       bus1_axi_ttlast ;
wire [ 7:0]bus1_axi_ttkeep ;
wire [63:0]bus1_axi_ttdata ;
wire       bus1_axi_ttready;
//wire [ 6:0]bus1_axi_ttuser ;
wire       bus1_axi_rtvalid;
wire       bus1_axi_rtlast1 ;
wire [ 7:0]bus1_axi_rtkeep ;
wire [63:0]bus1_axi_rtdata ;
wire [89:0]bus1_axi_rtuser ;
wire       bus1_axi_rtready;
wire       np_bus1_axi_rtready;
wire       bus2_axi_ttvalid;
wire       bus2_axi_ttlast ;
wire [ 7:0]bus2_axi_ttkeep ;
wire [63:0]bus2_axi_ttdata ;
wire       bus2_axi_ttready;
//wire [ 6:0]bus2_axi_ttuser ;
wire       bus2_axi_rtvalid;
wire       bus2_axi_rtlast ;
wire [ 7:0]bus2_axi_rtkeep ;
wire [63:0]bus2_axi_rtdata ;
wire [89:0]bus2_axi_rtuser ;
wire       bus2_axi_rtready;
wire       np_bus2_axi_rtready;
wire       bus3_axi_ttvalid;
wire       bus3_axi_ttlast ;
wire [ 7:0]bus3_axi_ttkeep ;
wire [63:0]bus3_axi_ttdata ;
wire       bus3_axi_ttready;
//wire [ 6:0]bus3_axi_ttuser ;
wire       bus3_axi_rtvalid;
wire       bus3_axi_rtlast ;
wire [ 7:0]bus3_axi_rtkeep ;
wire [63:0]bus3_axi_rtdata ;
wire [89:0]bus3_axi_rtuser ;
wire       bus3_axi_rtready;
wire       np_bus3_axi_rtready;
wire         jtag_clk_n;

wire       np_bus0_axi_ttvalid;
wire       np_bus0_axi_ttlast ;
wire [ 7:0]np_bus0_axi_ttkeep ;
wire [63:0]np_bus0_axi_ttdata ;
wire       np_bus0_axi_ttready;
//wire [ 6:0]np_bus0_axi_ttuser ;
wire       np_bus1_axi_ttvalid;
wire       np_bus1_axi_ttlast ;
wire [ 7:0]np_bus1_axi_ttkeep ;
wire [63:0]np_bus1_axi_ttdata ;
wire       np_bus1_axi_ttready;
//wire [ 6:0]np_bus1_axi_ttuser ;
wire       np_bus2_axi_ttvalid;
wire       np_bus2_axi_ttlast ;
wire [ 7:0]np_bus2_axi_ttkeep ;
wire [63:0]np_bus2_axi_ttdata ;
wire       np_bus2_axi_ttready;
//wire [ 6:0]np_bus2_axi_ttuser ;
wire       np_bus3_axi_ttvalid;
wire       np_bus3_axi_ttlast ;
wire [ 7:0]np_bus3_axi_ttkeep ;
wire [63:0]np_bus3_axi_ttdata ;
wire       np_bus3_axi_ttready;
//wire [ 6:0]np_bus3_axi_ttuser ;

//40G
//********************************************************************
// AHB channel select
  // UDP config subsystem
    // output
  wire [31:0]      UDP_config_haddr_m       ;
  wire [31:0]      UDP_config_hwdata_m      ;
  wire             UDP_config_hwrite_m      ;
  wire [2:0]       UDP_config_hsize_m       ;
  wire [2:0]       UDP_config_hburst_m      ;
  wire [1:0]       UDP_config_htrans_m      ;
  wire [3:0]       UDP_config_hmaster_m     ; // only for AHB-5
  wire             UDP_config_hnonsec_m     ; // only for AHB-5
  wire             UDP_config_hexcl_m       ; // only for AHB-5
  wire             UDP_config_hmasterlock_m ; // only for AHB-5
  wire [6:0]       UDP_config_hprot_m       ;
    // input 
  wire [31:0]      UDP_config_hrdata_m      ;
  wire             UDP_config_hready_m      ;
  wire             UDP_config_hresp_m       ;

  // np ahb top
  wire            np_hselx_ahbm             ;
  wire            np_hready_ahbm            ;
  wire [1:0]      np_htrans_ahbm            ;
  wire [2:0]      np_hsize_ahbm             ;
  wire            np_hwrite_ahbm            ;
  wire [31:0]     np_haddr_ahbm             ;
  wire [31:0]     np_hwdata_ahbm            ;

  wire [2:0]      np_hburst_ahbm            ;
  wire [3:0]      np_hprot_ahbm             ;
  wire [31:0]     np_hrdata_ahbm            ; // output
  wire            np_hreadyout_ahbm         ; // output
  wire            np_hresp_ahbm             ; // output

  reg  [2:0]      np_rd_data_vld_shift;
  reg             phy_rd_process;
  reg             phy_rd_ack_h;
  reg             phy_rd_ack_h2;
  wire            phy_rd_ack;
  wire            phy_hreadyout;

  // wzk add here,for distinguish where rdata from
// ============================================================
//wire [31:0]hrdata_np_top;
//reg  [31:0]haddr_temp_reg;
//
//always @(posedge ahbclk or negedge ahbresetn)
// if(~ahbresetn)
//  haddr_temp_reg <= 32'h00000000;
// else if(np_hselx_ahbm)
//  haddr_temp_reg <= np_haddr_ahbm;
// else if(~np_hready_ahbm)
//  haddr_temp_reg <= haddr_temp_reg; 
// else
//  haddr_temp_reg <= 32'h00000000;
//
//assign np_hrdata_ahbm = ( haddr_temp_reg[19:16] == 4'b1111 ) ? 
//                      ( haddr_temp_reg[20] == 1'b0 ? hrdata_np_dma_0 : hrdata_np_dma_1 ) : hrdata_np_top;

// assign np_hrdata_ahbm = (haddr_temp_reg[31:20] == NP_DMA0_BASE_ADDR[31:20]) ? 
//                       (haddr_temp_reg[19:16] == NP_DMA0_BASE_ADDR[19:16] ? hrdata_np_dma_0 : hrdata_np_dma_1) : hrdata_np_top;

// ============================================================
  assign np_haddr_ahbm        = (external_ahb_select) ? haddr_ahbm        : UDP_config_haddr_m    ;
  assign np_hwdata_ahbm       = (external_ahb_select) ? hwdata_ahbm       : UDP_config_hwdata_m   ;
  assign np_hwrite_ahbm       = (external_ahb_select) ? hwrite_ahbm       : UDP_config_hwrite_m   ;
  assign np_hsize_ahbm        = (external_ahb_select) ? hsize_ahbm        : UDP_config_hsize_m    ;
  assign np_hburst_ahbm       = (external_ahb_select) ? hburst_ahbm       : UDP_config_hburst_m   ;
  assign np_htrans_ahbm       = (external_ahb_select) ? htrans_ahbm       : UDP_config_htrans_m   ;
  assign np_hprot_ahbm        = (external_ahb_select) ? hprot_ahbm        : UDP_config_hprot_m[3:0] ;
  assign np_hready_ahbm       = (external_ahb_select) ? hready_ahbm       : np_hreadyout_ahbm     ;
  assign np_hselx_ahbm        = (external_ahb_select) ? hselx_ahbm        : 1'b1 ;
    // external AHB return
  assign hrdata_ahbm          = (external_ahb_select) ? np_hrdata_ahbm    : 32'hFEDC_BA90 ;
  assign hreadyout_ahbm       = (external_ahb_select) ? np_hreadyout_ahbm : 1'b1;//1'b0 ;wzk,0615
  assign hresp_ahbm           = (external_ahb_select) ? np_hresp_ahbm     : 1'b0 ;
    // UDP system return
  assign UDP_config_hrdata_m  = (external_ahb_select) ? 32'hFEDC_BA90     : np_hrdata_ahbm ;
  assign UDP_config_hready_m  = (external_ahb_select) ? 1'b0              : np_hreadyout_ahbm ;
  assign UDP_config_hresp_m   = (external_ahb_select) ? 1'b0              : np_hresp_ahbm ;

  assign phy_hreadyout        = phy_rd_process ? phy_rd_ack : np_hreadyout_ahbm;

always @(posedge ahbclk or negedge ahbresetn) begin
  if(~ahbresetn)
    phy_rd_process <= 1'b0;
  else if(phy_rd_ack_h2)
    phy_rd_process <= 1'b0;
  else if((np_haddr_ahbm[18:12] >= `PHY_HEAD_BASE_ADDR) & (np_haddr_ahbm[18:12] <= `PHY_TAIL_BASE_ADDR) & np_hselx_ahbm & ~np_hwrite_ahbm & np_htrans_ahbm[1])
    phy_rd_process <= 1'b1;
  else
    phy_rd_process <= phy_rd_process;
end

always @(posedge ahbclk or negedge ahbresetn) begin
  if(~ahbresetn) begin
    phy_rd_ack_h <= 1'b0;
    phy_rd_ack_h2 <= 1'b0;
  end
  else begin
    phy_rd_ack_h <= |np_rd_data_vld_shift;
    phy_rd_ack_h2 <= phy_rd_ack_h;
  end
end

always @(posedge pkt_clk or negedge pkt_rstn) begin
  if(~pkt_rstn)
    np_rd_data_vld_shift <= 3'b000;
  else
    np_rd_data_vld_shift <= {np_rd_data_vld_shift[1:0],bus1_npsys_data_out_vld | bus2_npsys_data_out_vld | bus3_npsys_data_out_vld | bus4_npsys_data_out_vld};
end

assign phy_rd_ack = phy_rd_process & phy_rd_ack_h2;

//********************************************************************

//********************************************************************
// UDP config channel
  // sub-system instance
  NP_1G_UDP_system U_NP_1G_UDP_system (
    .clk_100M               (clk_100M                 ) ,
    .clk_125M               (clk_125M                 ) ,
    .clk_125M_90phase       (clk_125M_90phase         ) ,
    .dcm_locked             (dcm_locked               ) ,

    .AHB_clk_125M           (ahbclk                   ) ,
    .reset                  (~ahbresetn               ) ,
    .ram_dp_cfg_register    (ram_dp_cfg_out_0         ) ,  //(ram_dp_cfg_register      ) ,
    .ram_2p_cfg_register    (ram_2p_cfg_out_0         ) ,  //(ram_2p_cfg_register      ) ,

    .AHB_haddr_m            (UDP_config_haddr_m       ) ,
    .AHB_hwdata_m           (UDP_config_hwdata_m      ) ,
    .AHB_hwrite_m           (UDP_config_hwrite_m      ) ,
    .AHB_hsize_m            (UDP_config_hsize_m       ) ,
    .AHB_hburst_m           (UDP_config_hburst_m      ) ,
    .AHB_htrans_m           (UDP_config_htrans_m      ) ,
    .AHB_hmaster_m          (UDP_config_hmaster_m     ) , // only for AHB-5
    .AHB_hnonsec_m          (UDP_config_hnonsec_m     ) , // only for AHB-5
    .AHB_hexcl_m            (UDP_config_hexcl_m       ) , // only for AHB-5
    .AHB_hmasterlock_m      (UDP_config_hmasterlock_m ) , // only for AHB-5
    .AHB_hprot_m            (UDP_config_hprot_m       ) ,
    .AHB_hrdata_m           (UDP_config_hrdata_m      ) ,
    .AHB_hready_m           (UDP_config_hready_m      ) ,
    .AHB_hresp_m            (UDP_config_hresp_m       ) ,

    .phyrst_n               (phyrst_n                 ) ,
    .rgmii_rx_clk           (rgmii_rx_clk             ) ,
    .rgmii_rx_ctrl          (rgmii_rx_ctrl            ) ,
    .rgmii_rxd              (rgmii_rxd                ) ,
    .rgmii_tx_clk           (rgmii_tx_clk             ) ,
    .rgmii_tx_ctrl          (rgmii_tx_ctrl            ) ,
    .rgmii_txd              (rgmii_txd                )
  ) ;
//********************************************************************
// Create a negative jtag clocks to deal with falling-edge flops
assign jtag_clk_n = ~jtag_clk;

//jtag
  np_32ME_jtag_top U_np_32ME_jtag_top(
    // Clocks and resets
    .cfg_clk            (pkt_clk        ),
    .cfg_rst            (~pkt_rstn      ),

    // JTAG interface    
    .jtag_trst          (jtag_trst  ),
    .jtag_tms           (jtag_tms   ),
    .jtag_tdi           (jtag_tdi   ),
    .jtag_tdo           (jtag_tdo_np   ),
    .jtag_tdo_en        (jtag_tdo_en_np),
    .jtag_clk           (jtag_clk   ),
    .jtag_clk_n         (jtag_clk_n ),

    // Scan Signals
    .scan_mode          (scan_mode   ),
    .scan_set_rst       (scan_set_rst),

    .cfg_addr_o         (jtag_cfg_addr_o   ),
    .cfg_wr_data_o      (jtag_cfg_wr_data_o),
    .cfg_wr_en_o        (jtag_cfg_wr_en_o  ),
    .cfg_rd_en_o        (jtag_cfg_rd_en_o  ),
    .cfg_rd_data_i      (jtag_cfg_rd_data_i),
    .jtag_occupy        (jtag_occupy        )
  );

  cpu_ahb_np_top u_np_ahb_top(
   .clk_sys           (pkt_clk),
   .rst_n_sys         (pkt_rstn),
    //AHB BUS
   .HRESETn           (ahbresetn),
   .HCLK              (ahbclk),
   .HSEL              (np_hselx_ahbm),
   .HADDR             (np_haddr_ahbm),
   .HTRANS            (np_htrans_ahbm),
   .HSIZE             (np_hsize_ahbm),
   .HBURST            (np_hburst_ahbm),
   .HPROT             (np_hprot_ahbm),
   .HWRITE            (np_hwrite_ahbm),
   .HREADYin          (np_hready_ahbm),
   .HWDATA            (np_hwdata_ahbm),
   .HRDATA            (np_hrdata_ahbm),//(hrdata_np_top),//(hrdata_ahbm),
   .HREADYout         (np_hreadyout_ahbm),
   .HRESP             (np_hresp_ahbm),
    // Scan Signals
    .scan_mode          (scan_mode   ),
    .scan_set_rst       (scan_set_rst),
    // phy read
    .phy_rd_process     (phy_rd_process),
    .phy_rd_ack         (phy_rd_ack),
    //with np  
   .np_addr_in (ahb_cfg_addr_o    ), 
   .np_data_in (ahb_cfg_wr_data_o ), 
   .np_wr      (ahb_cfg_wr_en_o   ), 
   .np_rd      (ahb_cfg_rd_en_o   ), 
   .np_data_out(ahb_cfg_rd_data_i )
  );

  phy_mac_interface u_phy_mac_interface(
    .clk                            ( pkt_clk                                           ),
    .rst_n                          ( pkt_rstn                                          ),
    .np_data_out                    ( phy_mac_data_out                                  ),
    .np_data_out_vld                ( phy_mac_data_out_vld                              ),
    .np_data_in                     ( phy_mac_data_in                                   ),
    .np_addr_in                     ( phy_mac_addr_in                                   ),
    .np_wr                          ( phy_mac_wr                                        ),
    .np_rd                          ( phy_mac_rd                                        ),
    // .bus1_np_addr_ctrl              ( {bus1_np_addr_ctrl[53:52],bus1_np_addr_ctrl[5:0]} ),
    // .bus2_np_addr_ctrl              ( {bus2_np_addr_ctrl[51:50],bus2_np_addr_ctrl[5:0]} ),
    // .bus3_np_addr_ctrl              ( {bus3_np_addr_ctrl[51:50],bus3_np_addr_ctrl[5:0]} ),
    // .bus4_np_addr_ctrl              ( {bus4_np_addr_ctrl[51:50],bus4_np_addr_ctrl[5:0]} ),
    .bus1_ack_register              ( bus1_ack_register                                 ),
    .bus1_mac_pcs_status_register0  ( bus1_mac_pcs_status_register0                     ),
    .bus1_mac_pcs_status_register2  ( bus1_mac_pcs_status_register2                     ),
    .bus1_mac_pcs_status_register7  ( bus1_mac_pcs_status_register7                     ),
    .bus1_mac_pcs_status_register8  ( bus1_mac_pcs_status_register8                     ),
    .bus1_reset_register            ( bus1_reset_register                               ),
    .bus1_phy_ctrl_register         ( bus1_phy_ctrl_register                            ),
    .bus1_req_lb_register           ( bus1_req_lb_register                              ),
    .bus1_mac_pcs_status_register1  ( bus1_mac_pcs_status_register1                     ),
    .bus1_mac_pcs_status_register3  ( bus1_mac_pcs_status_register3                     ),
    .bus1_mac_pcs_status_register4  ( bus1_mac_pcs_status_register4                     ),
    .bus1_mac_pcs_status_register5  ( bus1_mac_pcs_status_register5                     ),
    .bus1_mac_pcs_status_register6  ( bus1_mac_pcs_status_register6                     ),
    .bus2_ack_register              ( bus2_ack_register                                 ),
    .bus2_mac_pcs_status_register0  ( bus2_mac_pcs_status_register0                     ),
    .bus2_mac_pcs_status_register2  ( bus2_mac_pcs_status_register2                     ),
    .bus2_mac_pcs_status_register7  ( bus2_mac_pcs_status_register7                     ),
    .bus2_mac_pcs_status_register8  ( bus2_mac_pcs_status_register8                     ),
    .bus2_reset_register            ( bus2_reset_register                               ),
    .bus2_phy_ctrl_register         ( bus2_phy_ctrl_register                            ),
    .bus2_req_lb_register           ( bus2_req_lb_register                              ),
    .bus2_mac_pcs_status_register1  ( bus2_mac_pcs_status_register1                     ),
    .bus2_mac_pcs_status_register3  ( bus2_mac_pcs_status_register3                     ),
    .bus2_mac_pcs_status_register4  ( bus2_mac_pcs_status_register4                     ),
    .bus2_mac_pcs_status_register5  ( bus2_mac_pcs_status_register5                     ),
    .bus2_mac_pcs_status_register6  ( bus2_mac_pcs_status_register6                     ),
    .bus3_ack_register              ( bus3_ack_register                                 ),
    .bus3_mac_pcs_status_register0  ( bus3_mac_pcs_status_register0                     ),
    .bus3_mac_pcs_status_register2  ( bus3_mac_pcs_status_register2                     ),
    .bus3_mac_pcs_status_register7  ( bus3_mac_pcs_status_register7                     ),
    .bus3_mac_pcs_status_register8  ( bus3_mac_pcs_status_register8                     ),
    .bus3_reset_register            ( bus3_reset_register                               ),
    .bus3_phy_ctrl_register         ( bus3_phy_ctrl_register                            ),
    .bus3_req_lb_register           ( bus3_req_lb_register                              ),
    .bus3_mac_pcs_status_register1  ( bus3_mac_pcs_status_register1                     ),
    .bus3_mac_pcs_status_register3  ( bus3_mac_pcs_status_register3                     ),
    .bus3_mac_pcs_status_register4  ( bus3_mac_pcs_status_register4                     ),
    .bus3_mac_pcs_status_register5  ( bus3_mac_pcs_status_register5                     ),
    .bus3_mac_pcs_status_register6  ( bus3_mac_pcs_status_register6                     ),
    .bus4_ack_register              ( bus4_ack_register                                 ),
    .bus4_mac_pcs_status_register0  ( bus4_mac_pcs_status_register0                     ),
    .bus4_mac_pcs_status_register2  ( bus4_mac_pcs_status_register2                     ),
    .bus4_mac_pcs_status_register7  ( bus4_mac_pcs_status_register7                     ),
    .bus4_mac_pcs_status_register8  ( bus4_mac_pcs_status_register8                     ),
    .bus4_reset_register            ( bus4_reset_register                               ),
    .bus4_phy_ctrl_register         ( bus4_phy_ctrl_register                            ),
    .bus4_req_lb_register           ( bus4_req_lb_register                              ),
    .bus4_mac_pcs_status_register1  ( bus4_mac_pcs_status_register1                     ),
    .bus4_mac_pcs_status_register3  ( bus4_mac_pcs_status_register3                     ),
    .bus4_mac_pcs_status_register4  ( bus4_mac_pcs_status_register4                     ),
    .bus4_mac_pcs_status_register5  ( bus4_mac_pcs_status_register5                     ),
    .bus4_mac_pcs_status_register6  ( bus4_mac_pcs_status_register6                     ),
    .bus1_xlpcs_reg_wren            ( bus1_xlpcs_reg_wren                               ),
    .bus1_xlpcs_reg_rden            ( bus1_xlpcs_reg_rden                               ),
    .bus1_xlpcs_reg_addr            ( bus1_xlpcs_reg_addr                               ),
    .bus1_xlpcs_reg_din             ( bus1_xlpcs_reg_din                                ),
    .bus1_xlpcs_reg_dout            ( bus1_xlpcs_reg_dout                               ),
    .bus1_xlpcs_reg_busy            ( bus1_xlpcs_reg_busy                               ),
    .bus1_xpcs_reg_wren             ( bus1_xpcs_reg_wren                                ),
    .bus1_xpcs_reg_rden             ( bus1_xpcs_reg_rden                                ),
    .bus1_xpcs_reg_addr             ( bus1_xpcs_reg_addr                                ),
    .bus1_xpcs_reg_din              ( bus1_xpcs_reg_din                                 ),
    .bus1_xpcs_reg_dout             ( bus1_xpcs_reg_dout                                ),
    .bus1_xpcs_reg_busy             ( bus1_xpcs_reg_busy                                ),
    .bus1_mac_reg_wren              ( bus1_mac_reg_wren                                 ),
    .bus1_mac_reg_rden              ( bus1_mac_reg_rden                                 ),
    .bus1_mac_reg_addr              ( bus1_mac_reg_addr                                 ),
    .bus1_mac_reg_din               ( bus1_mac_reg_din                                  ),
    .bus1_mac_reg_dout              ( bus1_mac_reg_dout                                 ),
    .bus1_mac_reg_busy              ( bus1_mac_reg_busy                                 ),
    .bus2_xlpcs_reg_wren            ( bus2_xlpcs_reg_wren                               ),
    .bus2_xlpcs_reg_rden            ( bus2_xlpcs_reg_rden                               ),
    .bus2_xlpcs_reg_addr            ( bus2_xlpcs_reg_addr                               ),
    .bus2_xlpcs_reg_din             ( bus2_xlpcs_reg_din                                ),
    .bus2_xlpcs_reg_dout            ( bus2_xlpcs_reg_dout                               ),
    .bus2_xlpcs_reg_busy            ( bus2_xlpcs_reg_busy                               ),
    .bus2_xpcs_reg_wren             ( bus2_xpcs_reg_wren                                ),
    .bus2_xpcs_reg_rden             ( bus2_xpcs_reg_rden                                ),
    .bus2_xpcs_reg_addr             ( bus2_xpcs_reg_addr                                ),
    .bus2_xpcs_reg_din              ( bus2_xpcs_reg_din                                 ),
    .bus2_xpcs_reg_dout             ( bus2_xpcs_reg_dout                                ),
    .bus2_xpcs_reg_busy             ( bus2_xpcs_reg_busy                                ),
    .bus2_mac_reg_wren              ( bus2_mac_reg_wren                                 ),
    .bus2_mac_reg_rden              ( bus2_mac_reg_rden                                 ),
    .bus2_mac_reg_addr              ( bus2_mac_reg_addr                                 ),
    .bus2_mac_reg_din               ( bus2_mac_reg_din                                  ),
    .bus2_mac_reg_dout              ( bus2_mac_reg_dout                                 ),
    .bus2_mac_reg_busy              ( bus2_mac_reg_busy                                 ),
    .bus3_xlpcs_reg_wren            ( bus3_xlpcs_reg_wren                               ),
    .bus3_xlpcs_reg_rden            ( bus3_xlpcs_reg_rden                               ),
    .bus3_xlpcs_reg_addr            ( bus3_xlpcs_reg_addr                               ),
    .bus3_xlpcs_reg_din             ( bus3_xlpcs_reg_din                                ),
    .bus3_xlpcs_reg_dout            ( bus3_xlpcs_reg_dout                               ),
    .bus3_xlpcs_reg_busy            ( bus3_xlpcs_reg_busy                               ),
    .bus3_xpcs_reg_wren             ( bus3_xpcs_reg_wren                                ),
    .bus3_xpcs_reg_rden             ( bus3_xpcs_reg_rden                                ),
    .bus3_xpcs_reg_addr             ( bus3_xpcs_reg_addr                                ),
    .bus3_xpcs_reg_din              ( bus3_xpcs_reg_din                                 ),
    .bus3_xpcs_reg_dout             ( bus3_xpcs_reg_dout                                ),
    .bus3_xpcs_reg_busy             ( bus3_xpcs_reg_busy                                ),
    .bus3_mac_reg_wren              ( bus3_mac_reg_wren                                 ),
    .bus3_mac_reg_rden              ( bus3_mac_reg_rden                                 ),
    .bus3_mac_reg_addr              ( bus3_mac_reg_addr                                 ),
    .bus3_mac_reg_din               ( bus3_mac_reg_din                                  ),
    .bus3_mac_reg_dout              ( bus3_mac_reg_dout                                 ),
    .bus3_mac_reg_busy              ( bus3_mac_reg_busy                                 ),
    .bus4_xlpcs_reg_wren            ( bus4_xlpcs_reg_wren                               ),
    .bus4_xlpcs_reg_rden            ( bus4_xlpcs_reg_rden                               ),
    .bus4_xlpcs_reg_addr            ( bus4_xlpcs_reg_addr                               ),
    .bus4_xlpcs_reg_din             ( bus4_xlpcs_reg_din                                ),
    .bus4_xlpcs_reg_dout            ( bus4_xlpcs_reg_dout                               ),
    .bus4_xlpcs_reg_busy            ( bus4_xlpcs_reg_busy                               ),
    .bus4_xpcs_reg_wren             ( bus4_xpcs_reg_wren                                ),
    .bus4_xpcs_reg_rden             ( bus4_xpcs_reg_rden                                ),
    .bus4_xpcs_reg_addr             ( bus4_xpcs_reg_addr                                ),
    .bus4_xpcs_reg_din              ( bus4_xpcs_reg_din                                 ),
    .bus4_xpcs_reg_dout             ( bus4_xpcs_reg_dout                                ),
    .bus4_xpcs_reg_busy             ( bus4_xpcs_reg_busy                                ),
    .bus4_mac_reg_wren              ( bus4_mac_reg_wren                                 ),
    .bus4_mac_reg_rden              ( bus4_mac_reg_rden                                 ),
    .bus4_mac_reg_addr              ( bus4_mac_reg_addr                                 ),
    .bus4_mac_reg_din               ( bus4_mac_reg_din                                  ),
    .bus4_mac_reg_dout              ( bus4_mac_reg_dout                                 ),
    .bus4_mac_reg_busy              ( bus4_mac_reg_busy                                 )
  );

  crossbar_4x4_top U_crossbar_4x4_top(
    .clk                        (pkt_clk                  ),
    .rst_n                      (pkt_rstn                 ),
    .ram_2p_cfg_register        (ram_2p_cfg_out_0         ) ,  //(ram_2p_cfg_register	  ),
    //fp_and_sch_top_0--crossbar_ctl_top_0
    .uni_tx_rdy00               (uni_tx_rdy00             ),
    .uni_tx_rdy01               (uni_tx_rdy01             ),
    .uni_tx_rdy02               (uni_tx_rdy02             ),
    .uni_tx_rdy03               (uni_tx_rdy03             ),
    .mul_tx_rdy00               (mul_tx_rdy00             ),
    .mul_tx_rdy01               (mul_tx_rdy01             ),
    .mul_tx_rdy02               (mul_tx_rdy02             ),
    .mul_tx_rdy03               (mul_tx_rdy03             ),
    .emac_data_in0              (emac_data_in0            ),
    .emac_data_wren0            (emac_data_wren0          ),
    .rx_address_dpram0          (rx_address_dpram0        ),
    .mac_dest_port_in0          (mac_dest_port_in0        ),
    .mul_indicate0              (mul_indicate0            ),
    //fp_and_sch_top_1--crossbar_ctl_top_1
    .uni_tx_rdy10               (uni_tx_rdy10             ),
    .uni_tx_rdy11               (uni_tx_rdy11             ),
    .uni_tx_rdy12               (uni_tx_rdy12             ),
    .uni_tx_rdy13               (uni_tx_rdy13             ),
    .mul_tx_rdy10               (mul_tx_rdy10             ),
    .mul_tx_rdy11               (mul_tx_rdy11             ),
    .mul_tx_rdy12               (mul_tx_rdy12             ),
    .mul_tx_rdy13               (mul_tx_rdy13             ),
    .emac_data_in1              (emac_data_in1            ),
    .emac_data_wren1            (emac_data_wren1          ),
    .rx_address_dpram1          (rx_address_dpram1        ),
    .mac_dest_port_in1          (mac_dest_port_in1        ),
    .mul_indicate1              (mul_indicate1            ),
     //fp_and_sch_top_2--crossbar_ctl_top_2
    .uni_tx_rdy20               (uni_tx_rdy20             ),
    .uni_tx_rdy21               (uni_tx_rdy21             ),
    .uni_tx_rdy22               (uni_tx_rdy22             ),
    .uni_tx_rdy23               (uni_tx_rdy23             ),
    .mul_tx_rdy20               (mul_tx_rdy20             ),
    .mul_tx_rdy21               (mul_tx_rdy21             ),
    .mul_tx_rdy22               (mul_tx_rdy22             ),
    .mul_tx_rdy23               (mul_tx_rdy23             ),
    .emac_data_in2              (emac_data_in2            ),
    .emac_data_wren2            (emac_data_wren2          ),
    .rx_address_dpram2          (rx_address_dpram2        ),
    .mac_dest_port_in2          (mac_dest_port_in2        ),
    .mul_indicate2              (mul_indicate2            ),
    //fp_and_sch_top_3--crossbar_ctl_top_3
    .uni_tx_rdy30               (uni_tx_rdy30             ),
    .uni_tx_rdy31               (uni_tx_rdy31             ),
    .uni_tx_rdy32               (uni_tx_rdy32             ),
    .uni_tx_rdy33               (uni_tx_rdy33             ),
    .mul_tx_rdy30               (mul_tx_rdy30             ),
    .mul_tx_rdy31               (mul_tx_rdy31             ),
    .mul_tx_rdy32               (mul_tx_rdy32             ),
    .mul_tx_rdy33               (mul_tx_rdy33             ),
    .emac_data_in3              (emac_data_in3            ),
    .emac_data_wren3            (emac_data_wren3          ),
    .rx_address_dpram3          (rx_address_dpram3        ),
    .mac_dest_port_in3          (mac_dest_port_in3        ),
    .mul_indicate3              (mul_indicate3            ),
    //with MAC0         
    .emac_rx_ready0             (emac_rx_ready0             ),
    .pkt_data_o_0               (pkt_data_i_40_0            ),
    .pkt_dval_o_0               (pkt_dval_i_40_0            ),
    .pkt_dsav_o_0               (/*pkt_dsav_o_0           */),
    .pkt_sop_o_0                (pkt_sop_i_40_0             ),
    .pkt_eop_o_0                (pkt_eop_i_40_0             ),
    .pkt_mod_o_0                (pkt_mod_i_40_0             ),
    //with MAC1                
    .emac_rx_ready1             (emac_rx_ready1             ),
    .pkt_data_o_1               (pkt_data_i_40_1            ),
    .pkt_dval_o_1               (pkt_dval_i_40_1            ),
    .pkt_dsav_o_1               (/*pkt_dsav_o_1           */),
    .pkt_sop_o_1                (pkt_sop_i_40_1             ),
    .pkt_eop_o_1                (pkt_eop_i_40_1             ),
    .pkt_mod_o_1                (pkt_mod_i_40_1             ),
    //with MAC2         
    .emac_rx_ready2             (emac_rx_ready2             ),
    .pkt_data_o_2               (pkt_data_i_10_0            ),
    .pkt_dval_o_2               (pkt_dval_i_10_0            ),
    .pkt_dsav_o_2               (/*pkt_dsav_o_2           */),
    .pkt_sop_o_2                (pkt_sop_i_10_0             ),
    .pkt_eop_o_2                (pkt_eop_i_10_0             ),
    .pkt_mod_o_2                (pkt_mod_i_10_0             ),
    //with MAC3         
    .emac_rx_ready3             (emac_rx_ready3             ),
    .pkt_data_o_3               (pkt_data_i_10_1            ),
    .pkt_dval_o_3               (pkt_dval_i_10_1            ),
    .pkt_dsav_o_3               (/*pkt_dsav_o_3           */),
    .pkt_sop_o_3                (pkt_sop_i_10_1             ),
    .pkt_eop_o_3                (pkt_eop_i_10_1             ),
    .pkt_mod_o_3                (pkt_mod_i_10_1             )
  );


//signal sync
np_reg_sync #(.wid(36)) 
ack_sync(
  .d_clk(pkt_clk),
  .rst_n(pkt_rstn),
  .din({bus1_ack_register_temp,bus2_ack_register_temp,bus3_ack_register_temp,bus4_ack_register_temp}),
  .dout({bus1_ack_register,bus2_ack_register,bus3_ack_register,bus4_ack_register})
  );

np_reg_sync #(.wid(112)) 
mac_pcs_status_register0_sync(
  .d_clk(pkt_clk),
  .rst_n(pkt_rstn),
  .din({bus1_mac_pcs_status_register0_temp,bus2_mac_pcs_status_register0_temp,bus3_mac_pcs_status_register0_temp,bus4_mac_pcs_status_register0_temp}),
  .dout({bus1_mac_pcs_status_register0,bus2_mac_pcs_status_register0,bus3_mac_pcs_status_register0,bus4_mac_pcs_status_register0})
  );

np_reg_sync #(.wid(68)) 
mac_pcs_status_register2_sync(
  .d_clk(pkt_clk),
  .rst_n(pkt_rstn),
  .din({bus1_mac_pcs_status_register2_temp,bus2_mac_pcs_status_register2_temp,bus3_mac_pcs_status_register2_temp,bus4_mac_pcs_status_register2_temp}),
  .dout({bus1_mac_pcs_status_register2,bus2_mac_pcs_status_register2,bus3_mac_pcs_status_register2,bus4_mac_pcs_status_register2})
  );

np_reg_sync #(.wid(128)) 
mac_pcs_status_register7_sync(
  .d_clk(pkt_clk),
  .rst_n(pkt_rstn),
  .din({bus1_mac_pcs_status_register7_temp,bus2_mac_pcs_status_register7_temp,bus3_mac_pcs_status_register7_temp,bus4_mac_pcs_status_register7_temp}),
  .dout({bus1_mac_pcs_status_register7,bus2_mac_pcs_status_register7,bus3_mac_pcs_status_register7,bus4_mac_pcs_status_register7})
  );

np_reg_sync #(.wid(128)) 
mac_pcs_status_register8_sync(
  .d_clk(pkt_clk),
  .rst_n(pkt_rstn),
  .din({bus1_mac_pcs_status_register8_temp,bus2_mac_pcs_status_register8_temp,bus3_mac_pcs_status_register8_temp,bus4_mac_pcs_status_register8_temp}),
  .dout({bus1_mac_pcs_status_register8,bus2_mac_pcs_status_register8,bus3_mac_pcs_status_register8,bus4_mac_pcs_status_register8})
  );

// *******************
// MAIN CORE
// *******************

reg  jtag_state;

//jtag_cpu_sel
  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)begin
        //ahb_cfg_rd_data_i   <= 32'h0;
        jtag_cfg_rd_data_i  <= 32'h0;
        np_data_in          <= 32'h0;
        np_addr_in          <= 32'h0;
        np_wr               <= 1'h0;
        np_rd               <= 1'h0;
        np_sel_en           <= 1'h0;
 
        np_data_in_1          <= 32'h0;
        np_addr_in_1          <= 32'h0;
    end else if(jtag_occupy)begin
        //ahb_cfg_rd_data_i   <= (ahb_cfg_addr_o == `ADDR_JTAG_OCCUPY) ? {30'h0,jtag_state,jtag_occupy} : 32'h0;
        jtag_cfg_rd_data_i  <= np_data_out;
        np_data_in          <= jtag_cfg_wr_data_o;
        np_addr_in          <= jtag_cfg_addr_o;
        np_wr               <= jtag_cfg_wr_en_o;
        np_rd               <= jtag_cfg_rd_en_o;
        np_sel_en           <= jtag_cfg_rd_en_o || jtag_cfg_wr_en_o;
        
        np_data_in_1        <= jtag_cfg_wr_data_o;
        np_addr_in_1        <= jtag_cfg_addr_o;
    end else begin
        //ahb_cfg_rd_data_i   <= np_data_out;
        jtag_cfg_rd_data_i  <= 32'h0;
        np_data_in          <= ahb_cfg_wr_data_o;
        np_addr_in          <= ahb_cfg_addr_o;
        np_wr               <= ahb_cfg_wr_en_o;
        np_rd               <= ahb_cfg_rd_en_o;
        np_sel_en           <= ahb_cfg_rd_en_o || ahb_cfg_wr_en_o;

        np_data_in_1          <= ahb_cfg_wr_data_o;
        np_addr_in_1          <= ahb_cfg_addr_o;
    end
  end

always@(posedge pkt_clk or negedge pkt_rstn)begin
    if(~pkt_rstn)begin
        ahb_cfg_rd_data_i   <= 32'h0;
    end else begin
        ahb_cfg_rd_data_i   <= (!(|np_addr_in[20:12]) & (np_addr_in[11:2] == `ADDR_JTAG_OCCUPY)) ? {30'h0,jtag_state,jtag_occupy} : np_data_out;
    end
end

always@(posedge pkt_clk or negedge pkt_rstn)begin
    if(~pkt_rstn)begin
        jtag_state <= 1'b0;
    end else if(!(|np_addr_in[20:12]) & (np_addr_in[11:2] == `ADDR_JTAG_OCCUPY) & np_wr) begin
        jtag_state <= np_data_in[0];
    end else begin
  jtag_state <= jtag_state;
    end
end

// assign np_sel_en_config = np_sel_en;
// assign np_data_in_config = np_data_in;
// assign np_addr_in_config = np_addr_in;
// assign np_wr_config = np_wr;
// assign np_rd_config = np_rd;

always@(posedge pkt_clk or negedge pkt_rstn)begin
    if(~pkt_rstn)begin
        np_data_in_d1 <= 32'h0;
        // np_data_in_d2 <= 32'h0;
    end else begin
        np_data_in_d1 <= np_data_in;
        // np_data_in_d1 <= np_data_in_config;
        // np_data_in_d2 <= np_data_in_d1;
    end
end

//--------------------------------------------------------
//phy mac
assign phy_mac_data_in  = np_data_in;
assign phy_mac_addr_in  = np_addr_in[20:2];
assign phy_mac_wr       = np_wr;
assign phy_mac_rd       = np_rd;
//--------------------------------------------------------

assign npsys_data_in     = np_data_in;
assign npsys_addr_in     = np_addr_in[18:2];
assign npsys_data_in_1   = np_data_in_1;
assign npsys_addr_in_1   = np_addr_in_1[18:2];

assign npsys_wr_in_bus1 = np_addr_in[20:19]==2'b00 ? np_wr : 1'b0;
assign npsys_rd_in_bus1 = np_addr_in[20:19]==2'b00 ? np_rd : 1'b0;
assign npsys_wr_in_bus2 = np_addr_in[20:19]==2'b01 ? np_wr : 1'b0;
assign npsys_rd_in_bus2 = np_addr_in[20:19]==2'b01 ? np_rd : 1'b0;

assign npsys_wr_in_bus3 = np_addr_in[20:19]==2'b10 ? np_wr : 1'b0;
assign npsys_rd_in_bus3 = np_addr_in[20:19]==2'b10 ? np_rd : 1'b0;
assign npsys_wr_in_bus4 = np_addr_in[20:19]==2'b11 ? np_wr : 1'b0;
assign npsys_rd_in_bus4 = np_addr_in[20:19]==2'b11 ? np_rd : 1'b0;

always@(posedge pkt_clk or negedge pkt_rstn)begin
  if(~pkt_rstn)
    np_data_out <= 32'b0;
  else if(bus1_npsys_data_out_vld)
    np_data_out <= bus1_npsys_data_out;
  else if(bus2_npsys_data_out_vld)
    np_data_out <= bus2_npsys_data_out;
  else if(bus3_npsys_data_out_vld)
    np_data_out <= bus3_npsys_data_out;
  else if(bus4_npsys_data_out_vld)
    np_data_out <= bus4_npsys_data_out;
  else if(phy_mac_data_out_vld)
    np_data_out <= phy_mac_data_out;
  `ifdef CPU
    else if(CPU_SRAM_rdata_vld)
      np_data_out <= CPU_SRAM_rdata;
  `endif
  else if(CPU_reg_rdata_vld)
    np_data_out <= CPU_reg_rdata;
  else
    np_data_out <= np_data_out;
end

//--------------------------------------------------------
//always @(posedge pkt_clk or negedge pkt_rstn) begin
//  if(~pkt_rstn)
//      config_done <= 1'b0;
//  else if (CPU_reg_wren&&np_addr_in[11:2]==`ADDR_CONFIG_DONE) 
//      config_done <= np_data_in[0];
//  else
//      config_done <= config_done ;
//end

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)begin
        CPU_reg_rden_d1 <= 1'b0;
        np_addr_in_d1 <= 32'b0;
    end else begin
        CPU_reg_rden_d1 <= CPU_reg_rden;
        np_addr_in_d1 <= np_addr_in;
    end
  end
//--------------------------------------------------
//top reg
  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)
        CPU_reg_wren <= 1'b0;
    else if(np_wr)
        CPU_reg_wren <= !(|np_addr_in[20:12]);
    else
        CPU_reg_wren <= 1'b0;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)
        CPU_reg_rden <= 1'b0;
    else if(np_rd)
        CPU_reg_rden <= !(|np_addr_in[20:12]);
    else
        CPU_reg_rden <= 1'b0;
  end
  // assign CPU_reg_wren = np_wr && !(|np_addr_in[18:12]);
  // assign CPU_reg_rden = np_rd && !(|np_addr_in[18:12]);
//-------------------------------------------------
`ifdef CPU
  assign CPU_SRAM_wren = np_wr && np_addr_in[20:19]==2'b00 && np_addr_in[18:12]>=`SRAM_BASE_ADDR;
  assign CPU_SRAM_wrdata = np_data_in;
  assign CPU_SRAM_addr = {6'b0,np_addr_in[11:2]};
  assign CPU_SRAM_rden = np_rd && np_addr_in[20:19]==2'b00 && np_addr_in[18:12]>=`SRAM_BASE_ADDR;

  always @(posedge pkt_clk or negedge pkt_rstn) begin//PD_IN_reg,sci_in_reg,cam_rxd_reg
                                                   //XIN_reg,event_mark_reg,IF_clk_reg,AHB_IIO_CS_reg,CPU_rstn_reg
    if(~pkt_rstn)
        cpu_rstn_register <= 32'h00000001;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_RSTN_REGISTERS) 
        cpu_rstn_register <= np_data_in_d1;
    // else
    //     cpu_rstn_register <= cpu_rstn_register ;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin//rxd_gpi_0_reg,rxd_uart_reg
    if(~pkt_rstn)
        cpu_rxd_register <= 6'b0;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_RXD_REGISTERS) 
        cpu_rxd_register <= np_data_in_d1[5:0];
    // else
    //     cpu_rxd_register <= cpu_rxd_register ;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin//scli_gpi_reg,sdai_gpi_reg
    if(~pkt_rstn)
        cpu_gpi_register <= 2'b0;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_GPI_REGISTERS) 
        cpu_gpi_register <= np_data_in_d1[1:0];
    // else
    //     cpu_gpi_register <= cpu_gpi_register ;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin//spi_rxd_reg,spis_clk_reg,spim0_miso_gp_reg,
                                                   //spim2_miso_gp_reg,spic5_csn_reg
    if(~pkt_rstn)
        cpu_spi_register <= 14'b0;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_SPI_REGISTERS) 
        cpu_spi_register <= np_data_in_d1[13:0];
    // else
    //     cpu_spi_register <= cpu_spi_register ;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin//dt_cs_fuse_rden_i_reg,prm_rstn_fuse_aen_i_reg
                                                   //dt_int_fuse_pgmen_i_reg,dtd_fuse_a_i_reg
    if(~pkt_rstn)
        cpu_fuse_register <= 11'b0;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_FUSE_REGISTERS) 
        cpu_fuse_register <= np_data_in_d1[10:0];
    // else
    //     cpu_fuse_register <= cpu_fuse_register ;
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin//if_data_adc_d_i_reg
    if(~pkt_rstn)
        cpu_if_data_adc_d_i_register <= 95'b0;
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_IF_DATA_ADC_D_I_REGISTER0) 
        cpu_if_data_adc_d_i_register <= {cpu_if_data_adc_d_i_register[95:32],np_data_in_d1};
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_IF_DATA_ADC_D_I_REGISTER1) 
        cpu_if_data_adc_d_i_register <= {cpu_if_data_adc_d_i_register[95:64],np_data_in_d1,cpu_if_data_adc_d_i_register[31:0]};
    else if (CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_CPU_IF_DATA_ADC_D_I_REGISTER2) 
        cpu_if_data_adc_d_i_register <= {np_data_in_d1,cpu_if_data_adc_d_i_register[63:0]};
    // else
    //     cpu_if_data_adc_d_i_register <= cpu_if_data_adc_d_i_register ;
  end
`endif
  // always @(posedge pkt_clk or negedge pkt_rstn) begin//pullup
  //                                                  //clk,arstn,tck,tms,trstn,tdi,nptck,nptms,nptrstn,nptdi
  //   if(~pkt_rstn)
  //       io_pullup_cfg_register <= 10'b0;
  //   else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_IO_PULLUP_CFG_REGISTER)
  //       io_pullup_cfg_register <= np_data_in_d1[9:0];
  //   // else
  //   //     io_pullup_cfg_register <= io_pullup_cfg_register;
  // end

  // always @(posedge pkt_clk or negedge pkt_rstn) begin//pulldown
  //                                                  //clk,arstn,tck,tms,trstn,tdi,nptck,nptms,nptrstn,nptdi
  //   if(~pkt_rstn)
  //       io_pulldown_cfg_register <= 10'h3ff;
  //   else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_IO_PULLDOWN_CFG_REGISTER)
  //       io_pulldown_cfg_register <= np_data_in_d1[9:0];
  //   // else
  //   //     io_pulldown_cfg_register <= io_pulldown_cfg_register;
  // end

  assign ram_2p_cfg_out_0 = mbist_test ? 10'h69  : ram_2p_cfg_register  ;
  assign ram_2p_cfg_out_1 = mbist_test ? 10'h69  : ram_2p_cfg_register_1;
  assign ram_dp_cfg_out_0 = mbist_test ? 12'h69a : ram_dp_cfg_register  ;
  assign ram_dp_cfg_out_1 = mbist_test ? 12'h69a : ram_dp_cfg_register_1;
  assign rf_2p_cfg_out_0  = mbist_test ? 7'h33   : rf_2p_cfg_register   ;
  assign rf_2p_cfg_out_1  = mbist_test ? 7'h33   : rf_2p_cfg_register_1 ;
  
  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn) begin
        ram_2p_cfg_register <= 10'h69;//10'hfd; // 2022.6.6, xym
        ram_2p_cfg_register_1 <= 10'h69;//10'hfd; // 2022.6.6, xym
        // ram_2p_cfg_register <= 10'h69; // 2022.5.15, xym
        // ram_2p_cfg_register <= 10'hff;
    end
    else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_RAM_2P_CFG_REGISTER) begin
        ram_2p_cfg_register <= np_data_in_d1[9:0];
        ram_2p_cfg_register_1 <= np_data_in_d1[9:0];
    end
    else begin
        ram_2p_cfg_register <= ram_2p_cfg_register;
        ram_2p_cfg_register_1 <= ram_2p_cfg_register_1;
    end
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn) begin
        ram_dp_cfg_register <= 12'h69a;
        ram_dp_cfg_register_1 <= 12'h69a;
    end
    else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_RAM_DP_CFG_REGISTER) begin
        ram_dp_cfg_register <= np_data_in_d1[11:0];
        ram_dp_cfg_register_1 <= np_data_in_d1[11:0];
    end
    else begin
        ram_dp_cfg_register <= ram_dp_cfg_register;
        ram_dp_cfg_register_1 <= ram_dp_cfg_register;
    end
  end

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn) begin
        rf_2p_cfg_register <= 7'h33;
        rf_2p_cfg_register_1 <= 7'h33;
    end
    else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_RF_2P_CFG_REGISTER) begin
        rf_2p_cfg_register <= np_data_in_d1[6:0];
        rf_2p_cfg_register_1 <= np_data_in_d1[6:0];
    end
    else begin
        rf_2p_cfg_register <= rf_2p_cfg_register;
        rf_2p_cfg_register_1 <= rf_2p_cfg_register_1;
    end
  end

//---------------------------------------------------------------
//dma channel sel , 2022.5.1 xym
//---------------------------------------------------------------
  reg [3:0] dma_channel_sel ;

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)
        dma_channel_sel <= 4'b0000;
    else if(CPU_reg_wren&&np_addr_in_d1[11:2]==`ADDR_DMA_CHANNEL_SEL)
        dma_channel_sel <= np_data_in_d1[3:0];
  end
  assign dma_channel_sel0 = dma_channel_sel[1:0];
  assign dma_channel_sel1 = dma_channel_sel[3:2];

  always @(posedge pkt_clk or negedge pkt_rstn) begin
    if(~pkt_rstn)begin
        CPU_reg_rdata <= 32'b0;
        CPU_reg_rdata_vld <= 1'b0;
    end else if(CPU_reg_rden) begin
        case(np_addr_in_d1[11:2])
        `ADDR_CONFIG_DONE                   :begin
            CPU_reg_rdata <= {28'b0,config_done};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ifdef CPU
        `ADDR_CPU_RSTN_REGISTERS            :begin
            CPU_reg_rdata <= cpu_rstn_register;
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_RXD_REGISTERS             :begin
            CPU_reg_rdata <= {26'b0,cpu_rxd_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_GPI_REGISTERS             :begin
            CPU_reg_rdata <= {30'b0,cpu_gpi_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_SPI_REGISTERS             :begin
            CPU_reg_rdata <= {30'b0,cpu_spi_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_FUSE_REGISTERS            :begin
            CPU_reg_rdata <= {18'b0,cpu_fuse_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_IF_DATA_ADC_D_I_REGISTER0 :begin
            CPU_reg_rdata <= cpu_if_data_adc_d_i_register[31:0];
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_IF_DATA_ADC_D_I_REGISTER1 :begin
            CPU_reg_rdata <= cpu_if_data_adc_d_i_register[63:32];
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_CPU_IF_DATA_ADC_D_I_REGISTER2 :begin
            CPU_reg_rdata <= cpu_if_data_adc_d_i_register[95:64];
            CPU_reg_rdata_vld <= 1'b1;
        end
        `endif
        // `ADDR_IO_PULLUP_CFG_REGISTER        :begin
        //     CPU_reg_rdata <= {22'b0,io_pullup_cfg_register};
        //     CPU_reg_rdata_vld <= 1'b1;
        // end
        // `ADDR_IO_PULLDOWN_CFG_REGISTER      :begin
        //     CPU_reg_rdata <= {22'b0,io_pulldown_cfg_register};
        //     CPU_reg_rdata_vld <= 1'b1;
        // end
        `ADDR_RAM_2P_CFG_REGISTER           :begin
            CPU_reg_rdata <= {22'b0,ram_2p_cfg_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_RAM_DP_CFG_REGISTER           :begin
            CPU_reg_rdata <= {20'b0,ram_dp_cfg_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_RF_2P_CFG_REGISTER            :begin
            CPU_reg_rdata <= {25'b0,rf_2p_cfg_register};
            CPU_reg_rdata_vld <= 1'b1;
        end
        `ADDR_DMA_CHANNEL_SEL               :begin
            CPU_reg_rdata <= {28'b0,dma_channel_sel};
            CPU_reg_rdata_vld <= 1'b1;
        end
        default                             :begin
            // CPU_reg_rdata <= CPU_reg_rdata;
            CPU_reg_rdata_vld <= 1'b0;
        end
        endcase
    end else begin
        // CPU_reg_rdata <= CPU_reg_rdata;
        CPU_reg_rdata_vld <= 1'b0;
    end
  end

// assign pkt_data_o_40_0 = (bus1_phy_ctrl_register[14])?  pkt_test_data_0:mac_data_o_40_0;
// assign pkt_eop_o_40_0  = (bus1_phy_ctrl_register[14])?  pkt_test_eop_0 :mac_eop_o_40_0 ;
// assign pkt_mod_o_40_0  = (bus1_phy_ctrl_register[14])?  5'b0           :mac_mod_o_40_0 ;
// assign pkt_sop_o_40_0  = (bus1_phy_ctrl_register[14])?  pkt_test_sop_0 :mac_sop_o_40_0 ;
// assign pkt_dval_o_40_0 = (bus1_phy_ctrl_register[14])?  pkt_test_dvld_0:mac_dval_o_40_0;
// assign pkt_dsav_o_40_0 = (bus1_phy_ctrl_register[14])?  pkt_test_dsav_0:mac_dsav_o_40_0;

// assign mac_data_i_40_0 = (bus1_phy_ctrl_register[15])?  pkt_test_data_0:pkt_data_i_40_0;
// assign mac_eop_i_40_0  = (bus1_phy_ctrl_register[15])?  pkt_test_eop_0 :pkt_eop_i_40_0 ;
// assign mac_mod_i_40_0  = (bus1_phy_ctrl_register[15])?  5'b0           :pkt_mod_i_40_0 ;
// assign mac_sop_i_40_0  = (bus1_phy_ctrl_register[15])?  pkt_test_sop_0 :pkt_sop_i_40_0 ;
// assign mac_dval_i_40_0 = (bus1_phy_ctrl_register[15])?  pkt_test_dvld_0:pkt_dval_i_40_0;

// assign pkt_data_o_40_1 = (bus2_phy_ctrl_register[14])?  pkt_test_data_1:mac_data_o_40_1;
// assign pkt_eop_o_40_1  = (bus2_phy_ctrl_register[14])?  pkt_test_eop_1 :mac_eop_o_40_1 ;
// assign pkt_mod_o_40_1  = (bus2_phy_ctrl_register[14])?  5'b0           :mac_mod_o_40_1 ;
// assign pkt_sop_o_40_1  = (bus2_phy_ctrl_register[14])?  pkt_test_sop_1 :mac_sop_o_40_1 ;
// assign pkt_dval_o_40_1 = (bus2_phy_ctrl_register[14])?  pkt_test_dvld_1:mac_dval_o_40_1;
// assign pkt_dsav_o_40_1 = (bus2_phy_ctrl_register[14])?  pkt_test_dsav_1:mac_dsav_o_40_1;

// assign mac_data_i_40_1 = (bus2_phy_ctrl_register[15])?  pkt_test_data_1:pkt_data_i_40_1;
// assign mac_eop_i_40_1  = (bus2_phy_ctrl_register[15])?  pkt_test_eop_1 :pkt_eop_i_40_1 ;
// assign mac_mod_i_40_1  = (bus2_phy_ctrl_register[15])?  5'b0           :pkt_mod_i_40_1 ;
// assign mac_sop_i_40_1  = (bus2_phy_ctrl_register[15])?  pkt_test_sop_1 :pkt_sop_i_40_1 ;
// assign mac_dval_i_40_1 = (bus2_phy_ctrl_register[15])?  pkt_test_dvld_1:pkt_dval_i_40_1;


// assign pkt_data_o_10_0 = (bus3_phy_ctrl_register[14])?  pkt_test_data_2:mac_data_o_10_0;
// assign pkt_eop_o_10_0  = (bus3_phy_ctrl_register[14])?  pkt_test_eop_2 :mac_eop_o_10_0 ;
// assign pkt_mod_o_10_0  = (bus3_phy_ctrl_register[14])?  5'b0           :mac_mod_o_10_0 ;
// assign pkt_sop_o_10_0  = (bus3_phy_ctrl_register[14])?  pkt_test_sop_2 :mac_sop_o_10_0 ;
// assign pkt_dval_o_10_0 = (bus3_phy_ctrl_register[14])?  pkt_test_dvld_2:mac_dval_o_10_0;
// assign pkt_dsav_o_10_0 = (bus3_phy_ctrl_register[14])?  pkt_test_dsav_2:mac_dsav_o_10_0;

// assign mac_data_i_10_0 = (bus3_phy_ctrl_register[15])?  pkt_test_data_2:pkt_data_i_10_0;
// assign mac_eop_i_10_0  = (bus3_phy_ctrl_register[15])?  pkt_test_eop_2 :pkt_eop_i_10_0 ;
// assign mac_mod_i_10_0  = (bus3_phy_ctrl_register[15])?  5'b0           :pkt_mod_i_10_0 ;
// assign mac_sop_i_10_0  = (bus3_phy_ctrl_register[15])?  pkt_test_sop_2 :pkt_sop_i_10_0 ;
// assign mac_dval_i_10_0 = (bus3_phy_ctrl_register[15])?  pkt_test_dvld_2:pkt_dval_i_10_0;


// assign pkt_data_o_10_1 = (bus4_phy_ctrl_register[14])?  pkt_test_data_3:mac_data_o_10_1;
// assign pkt_eop_o_10_1  = (bus4_phy_ctrl_register[14])?  pkt_test_eop_3 :mac_eop_o_10_1 ;
// assign pkt_mod_o_10_1  = (bus4_phy_ctrl_register[14])?  5'b0           :mac_mod_o_10_1 ;
// assign pkt_sop_o_10_1  = (bus4_phy_ctrl_register[14])?  pkt_test_sop_3 :mac_sop_o_10_1 ;
// assign pkt_dval_o_10_1 = (bus4_phy_ctrl_register[14])?  pkt_test_dvld_3:mac_dval_o_10_1;
// assign pkt_dsav_o_10_1 = (bus4_phy_ctrl_register[14])?  pkt_test_dsav_3:mac_dsav_o_10_1;

// assign mac_data_i_10_1 = (bus4_phy_ctrl_register[15])?  pkt_test_data_3:pkt_data_i_10_1;
// assign mac_eop_i_10_1  = (bus4_phy_ctrl_register[15])?  pkt_test_eop_3 :pkt_eop_i_10_1 ;
// assign mac_mod_i_10_1  = (bus4_phy_ctrl_register[15])?  5'b0           :pkt_mod_i_10_1 ;
// assign mac_sop_i_10_1  = (bus4_phy_ctrl_register[15])?  pkt_test_sop_3 :pkt_sop_i_10_1 ;
// assign mac_dval_i_10_1 = (bus4_phy_ctrl_register[15])?  pkt_test_dvld_3:pkt_dval_i_10_1;

endmodule


module np_reg_sync #(
    parameter wid = 1
  )
  (
    input wire d_clk,
    input wire rst_n,
    input wire [wid-1:0] din,
    output reg [wid-1:0] dout
 );
  reg [wid-1:0] dout_temp;

  always @(posedge d_clk or negedge rst_n) begin
    if (~rst_n) begin
       dout_temp     <= 'b0;
       dout          <= 'b0;   
    end
    else begin
       dout_temp     <= din;
       dout          <= dout_temp;
    end
  end
endmodule
